CPE380 Simple Processor Architecture Simulator

This is a cycle-by-cycle simulator for the simple architectural implementation described at http://aggregate.org/CPE380/simple.html.

Enter/edit your control and initialization here:

A maximum of 10 clock cycles will be simulated.

Memory latency will be 3 clock cycles.


The final status was a 56% match for that specified.

The following values were wrong: PC MEM[0x8]


The C program that generated this page was written by Hank Dietz using the CGIC library to implement the CGI interface.


CPE380 Computer Organization and Design.